The use of PMOS transistors in the input stage results in common-mode input-voltage capability down to 0. A CMOS transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal at very high values of load impedance , is employed as the output circuit. They can be phase compensated with a single external capacitor, and have terminals for adjustment of offset voltage for applications requiring offset-null capability. Terminal provisions are also made to permit strobing of the output stage. Typ - Very Low II.
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